Transmute Patents

The following are a partial list of patents granted to Transmute by the US PTO. Transmute has more patents granted and pending in the US and other countries. Please contact Transmute for information on patent licensing. 

US Patent 8,541,757B1
Accelerator on a chip having a cold ion source

Grant date 2013-09-24

An assembly includes a cold ion source and a chip. The cold ion source is fixed to the chip so that ions from the ion source can enter an acceleration channel in the chip. In one specific example, the ion source includes an ion exchange membrane that produces cold ions in that the ions as produced have an energy of less than 30 eV. The chip includes a substrate (such as a semiconductor substrate or a glass substrate) and a dielectric layer disposed on substrate, where the acceleration channel is a channel formed into the dielectric layer. In one specific example, the assembly is part of a Direct Write On Wafer (DWOW) printing system. The DWOW printing system is useful in semiconductor processing in that it can direct write an image onto a 300 mm diameter wafer in one minute.

US Patent 8,564,225 B1
Accelerator on a chip having a grid and plate cell

Grant date 2013-10-22

An accelerator assembly includes an acceleration channel that passes in a straight line through a plurality of accelerator cells. Each cell includes an acceleration region and a drift region. The drift region includes a high voltage plate and a grid electrode, where the grid electrode is disposed between the high voltage plate and the channel. In each cell, a large DC voltage is present on the high voltage plate. A voltage on the grid electrode is controlled such that at a first time an ion in the channel is attracted toward the high voltage plate, and such that at a second time the ion is shielded and is not attracted toward the high voltage plate. In one specific example, the assembly is part of a Direct Write On Wafer (DWOW) printing system that can direct write an image onto a 300 mm diameter wafer in one minute.

US Patent 8519644B1
Accelerator having acceleration channels formed between covalently bonded chips

Grant date 2013-08-27

An accelerator assembly includes a first chip and a second chip. An acceleration channel is formed into a surface of a first side of the first chip. The first side of the first chip is covalently bonded to a first side of the second chip such that the channel is a tubular void between the first and second chips. The channel has a tubular inside sidewall surface, substantially no portion of which is a metal surface. The channel has length-to-width ratio greater than five, and a channel width less than one micron. There are many substantially identical channels that extend in parallel between the first and second chips. In one specific example, the assembly is part of a Direct Write On Wafer (DWOW) printing system. The DWOW printing system is useful in semiconductor processing in that it can direct write an image onto a 300 mm diameter wafer in one minute.

US Patent 8648315B1
Accelerator having a multi-channel micro-collimator

Grant date 2014-02-11

An ion accelerator includes a plasma ion source and a micro-collimator. The micro-collimator has a plurality of channels. The length-to-width ratio of each channel is greater than five, and the channel width is less than one micron. The ion source is coupled to the micro-collimator such that ions from the ion source pass into the channels, and then through the plurality of channels. In one specific example, the ion source produces cold ions that have only a small amount of lateral momentum. Each channel is an individually gated acceleration channel that is formed into a solid dielectric material. Ions are accelerated down the acceleration channel. The ion accelerator forms a part of an ionjet head of a Direct Write On Wafer (DWOW) printing system. The DWOW printing system is useful in semiconductor processing in that it can direct write an image onto a 300 mm diameter wafer in one minute.